Manufacturers of integrated circuits migrate to increasingly smaller geometries of semiconductor processing technologies in an attempt to reduce cost and improve product performance. Advances in processing technologies are typically accompanied by reductions in circuit element characteristics, such as channel length, metal pitch, diffusion spacing, and gate oxide thickness. However, as explained in detail below, these advances in processing technologies do not necessarily result in reductions of the voltage levels required by these integrated circuits.
Integrated circuits, such as Complex Programmable Logic Devices (CPLDs), typically contain one or more non-volatile memory arrays (e.g., EPROM, EEPROM, or Flash EPROM arrays) which are used to make connections, implement logic functions, and store the user-defined configuration of the logic device. A memory cell of a non-volatile memory array has an associated state which is defined by the threshold voltage of the memory cell. The threshold voltage of the memory cell is dependent on the amount of charge stored by the floating gate of the memory cell. The state of the memory cell is changed by altering this charge stored by the floating gate.
The alteration of charge stored by the floating gate is accomplished by applying high voltages across the terminals of the memory cell such that electrons are either transferred to or removed from the floating gate of the memory cell. High voltages are considered to be those voltages in excess of the supply voltage Vcc. When electrons are transferred to the floating gate, the effective threshold voltage of the memory cell is raised. A memory cell with a high threshold voltage, for purposes of this discussion, is said to be erased. This erasure may be accomplished by applying a large voltage delta across the control gate terminal and the source terminal (and well) of the memory cell. Conversely, when electrons are removed from the floating gate of the memory cell, the effective threshold voltage of the memory cell is lowered. A memory cell with a low threshold voltage, for purposes of this discussion, is said to be programmed. Programming may be accomplished by applying a large voltage delta across the control gate terminal and the drain terminal of the memory cell. In some cases, the voltage delta required to create this transfer of electrons can be 16 to 20 Volts or more. Thus, the programming and erasing of memory cells is a high voltage application.
To provide the high voltages to the memory cells, a CPLD requires some high voltage NMOS and PMOS circuit elements that are able to withstand these high voltages. High voltage circuit elements are those elements that are optimized for performance at voltages above the Vcc power supply of the logic device to 12-14 Volts. High voltage circuit elements are typically manufactured with thicker gate oxides and longer channel lengths than low voltage circuit elements, among other differences, that make them suitable for use in circuits with high voltage applications.
To lessen the voltage requirements for high voltage circuit elements, some manufacturers have migrated to a positive and negative voltage scheme to program and erase memory cells. For example, if a 16 Volt delta is required across the control gate and drain to program a memory cell, the memory cell may receive a grounding voltage of 0 Volts applied to the control gate terminal and +16 Volts applied to the drain terminal. However, the same 16 Volt delta in the positive and negative voltage scheme may be accomplished by applying -8 Volts to the control gate terminal and applying +8 Volts to the drain terminal. Typically, in this scheme, different circuit elements transmit positive and negative voltages. Thus, a single high voltage circuit element only tolerates a portion (e.g., 8 Volts or -8 Volts) of the voltage (e.g., 16 Volts) required to program the memory cell. As a result, only the memory cell undergoing the operation is subjected to the full voltage differential.
Unfortunately, the use of negative high voltages makes the design of logic devices much more complicated. For classically trained integrated circuit designers, it is conceptually and logistically much easier to deal with positive voltages. The vast majority of digital integrated circuit designs are based on a V.sub.CC (the supply voltage level of 5 Volts, 3.3 Volts, etc.) and GND (the 0 Volt ground) scheme, which represent logic high and logic low levels, respectively. As a result, an issue arises as to how to "control" and "translate" the negative voltage levels into standard CMOS levels of V.sub.CC and GND for interpretation by the rest of the circuit elements in the logic device. For example, it may be necessary to determine when the negative high voltage has reached a certain level below GND, and to provide that information to a low voltage circuit element in the form of a standard CMOS logic level of V.sub.CC or GND. A circuit accomplishing this function is called a Negative Voltage Detector.
FIG. 1 is a schematic diagram of a conventional Negative Voltage Detector (NVD) 100. NVD 100 includes a reference voltage generator 101, a negative charge pump 102, and a comparator circuit 103.
The output voltage of reference voltage generator 101, V.sub.REF, is regulated to a fixed negative reference voltage using a conventional method. Voltage V.sub.REF is provided to the positive input terminal of comparator circuit 103. The negative supply voltage, V.sub.NN, is provided to the negative input terminal of comparator circuit 103. Note that voltage V.sub.NN is the voltage of interest, and that voltage V.sub.REF is the voltage to which voltage V.sub.NN will be compared. Comparator circuit 103 is supplied by the standard nominal supply voltage V.sub.CC (e.g., a logic high value) and GND (e.g., a logic low value) supply rails. Thus, the output voltage of comparator circuit 103, V.sub.COMP, will be either a logic low or a logic high value, depending whether voltage V.sub.NN is more or less negative than voltage V.sub.REF.
For example, when voltage V.sub.NN is less negative than voltage V.sub.REF, the output voltage V.sub.COMP will have a logic low value. However, when voltage V.sub.NN is equal to or more negative than voltage V.sub.REF, the output voltage V.sub.COMP will have a logic high value. In this way, a negative detection of voltage level V.sub.NN voltage level can be achieved and translated into a useable standard CMOS logic level.
Unfortunately, NVD 100 is very costly in terms of device area used. Charge pumps and comparators require many, often large, devices for implementation. If local detection of many different negative voltages is required around the logic device, then constraints on available area would prohibit this type of NVD.
It would be useful to provide a simple circuit for detecting a negative voltage level. In particular, it would be useful to provide an NVD that uses very few small devices that can be reproduced many times throughout the chip wherever local detection of a negative voltage level is required.